1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of a dielectric interlayer including highly stressed materials to enhance performance of field effect transistors.
2. Description of the Related Art
During the fabrication of integrated circuits, a large number of circuit elements are formed on a given chip area according to a specified circuit layout. One important circuit element in modern semiconductor devices is the field effect transistor. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost effectiveness. During the fabrication of complex integrated circuits using CMOS technology, millions of field effect transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semi-conductor layer, such as a silicon-based layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the “wiring,” i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of conductive lines, such as polysilicon and the like, within the device layer so that one or more additional “wiring” layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in advanced devices, low-k materials having a permittivity of 3.0 or less are used. The metal lines and the surrounding dielectric material will be referred to hereinafter as a metallization layer. Between two stacked adjacent metallization layers and also between the device layer and the first metallization layer, respective dielectric interlayers are formed through which metal-filled openings are formed to establish the electrical connection between metal lines of the adjacent metallization layers or between circuit elements and metal lines of the first metallization layer. In typical applications, the dielectric interlayer separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited above a dielectric etch stop layer by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates.
Due to the continuous device scaling, resulting in gate length of MOS transistors on the order of magnitude of 50 nm and less, further performance enhancement of the individual transistors may be difficult to achieve, since a reduced gate length typically requires an adaptation of the silicon dioxide based gate insulation layer which controls the capacitive coupling between the gate electrode and the channel region. Since the thickness of the silicon dioxide based gate insulation layer has now reached 2 nm and less, a further reduction of the thickness thereof may be accompanied by significant performance degradation due to leakage currents, as the amount of leakage currents may exponentially depend on the thickness of the silicon dioxide based insulating layer. Thus, unless sophisticated high-k dielectric materials may be implemented in the overall CMOS process flow, further device scaling may be associated with a less pronounced performance gain due to the reduced controllability of the channel, if the gate oxide thickness is substantially maintained. Therefore, it has been proposed to further enhance the transistor performance by inducing an appropriate type of strain in the channel regions of the transistors in order to significantly modify the charge carrier mobility. For example, for a standard crystallographic orientation of a silicon-based semiconductor layer, that is, when the silicon represents a silicon material having a surface orientation (100) with the channel length oriented along a <110> direction, a compressive strain in the channel region may result in an improvement of the hole mobility, while a tensile strain may result in an increase of the electron mobility. The enhanced charge carrier mobility thus directly translates into enhanced transistor performance with respect to current drive capability and operating speed. Thus, a plurality of different mechanisms has been developed to obtain the desired type and magnitude of strain in the respective channel regions.
One efficient mechanism in generating strain in a transistor device is the deposition of highly stressed dielectric materials above the individual transistor elements, wherein the highly stressed dielectric material may then act on the transistor structure to provide the desired type of strain in the channel region. Since the contact etch stop layer is positioned close to the channel region and since silicon nitride, nitrogen-enriched silicon carbide and the like, which are frequently used materials for the contact etch stop layer, may be deposited with high internal stress levels, respective manufacturing schemes have been developed to position an appropriately stressed contact etch stop layer above the transistor element under consideration. That is, a contact etch stop material may be positioned above P-channel transistors with a high internal stress level, which may also be referred to as compressive stress, to induce a specific type of strain in order to enhance the hole mobility of P-channel transistors. For example, compressive stress levels of up to 3 GPa and higher may be achieved on the basis of PECVD techniques by appropriately controlling the deposition parameters. Similarly, the contact etch stop material above N-channel transistors may be provided with high internal tensile stress, thereby reaching values of up to 2 GPa and higher, which may result in an appropriate strain in the channel region for increasing the electron mobility. The deposition of the appropriately stressed etch material above P-channel transistors and N-channel transistors may be accomplished on the basis of well-established masking regimes. For instance, the compressively stressed dielectric material may be deposited first, and may then be selectively removed above the N-channel transistor, followed by the deposition of the tensilely stressed material which may then be selectively removed from above the P-channel transistor. Similarly, a process sequence may be used in which the tensilely stressed material is deposited first, then selectively removed from above the P-channel transistor, followed by a further deposition and selective patterning process for the material having the compressive stress. Depending on the process and device requirements, the patterning of the dielectric materials of different internal stress may be associated with the deposition of appropriate etch stop materials or etch indicator materials, for instance in the form of silicon dioxide and the like.
As previously discussed, highly advanced semiconductor devices having transistor elements with gate lengths of 50 nm and less may also include distances between neighboring circuit elements, such as gate electrodes, which may also be scaled down in correlation with the gate length, thereby obtaining values of 200 nm and significantly less, resulting in a space of 100 nm or less between densely packed gate electrode structures. Thus, although these techniques are highly desirable in view of the stress transfer mechanism provided by the highly stressed etch stop material, the gap fill capabilities of the high rate PECVD techniques for the deposition of the silicon nitride material may be taken into consideration, thereby imposing significant constraints on the overall process flow for forming the etch stop material and also for the interlayer dielectric material, which may typically be provided in the form of silicon dioxide. That is, an appropriate deposition technique has to be used to reliably form the interlayer dielectric material above the pronounced surface topography created by the subsequent complex deposition sequence for forming the highly stressed etch stop materials of different intrinsic stress.
For this reason, usually the interlayer dielectric material may be deposited, at least immediately above the highly stressed etch stop material, by a deposition technique having a significantly enhanced gap fill capability so as to avoid the creation of deposition irregularities, such as voids in the deposited material. The silicon dioxide-based material may therefore be formed by a thermal chemical vapor deposition (CVD) process on the basis of TEOS and ozone, which generates a silicon dioxide film exhibiting excellent gap fill capabilities, that is, this deposition technique provides even for a “flow-like” behavior, thereby allowing the reliable filling of empty spaces between closely spaced circuit elements, such as gate electrode structures. In view of the layer and deposition characteristics, the thermal CVD process is typically performed at significantly higher pressures compared to PECVD techniques, for example, in the range of 200-760 Torr, and this deposition process is therefore denoted as “sub-atmospheric CVD” (SACVD). However, the material and process characteristics of the SACVD oxide may differ significantly from PECVD oxide in terms of mechanical integrity and deposition rate. Consequently, in some process strategies, a PECVD oxide may be formed above the SACVD oxide to enhance the characteristics of the overall interlayer dielectric material and provide enhanced process reliability during a subsequent planarization process, for instance, on the basis of a chemical mechanical polishing (CMP) process. A substantially planar surface topography may represent an important aspect during the further processing of the semiconductor device, since the subsequent lithography process and the following contact etch process may be influenced by the surface topography as well as by the material composition of the complex interlayer dielectric stack, in particular if highly scaled semiconductor devices are considered.
With reference to FIG. 1, the problems involved in forming an interlayer dielectric stack for advanced semiconductor devices will now be described in more detail. FIG. 1 schematically illustrates a semiconductor device 100 comprising a substrate 101 that may represent a bulk silicon substrate or a silicon-on-insulator (SOI) substrate having formed thereon a device layer or semiconductor layer 102. The semiconductor layer 102 may be a silicon-based material, whose mobility characteristics of the respective charge carriers may be adjusted on the basis of strain induced therein according to the principles described above. It should be appreciated that, for an SOI configuration, the substrate 101 may comprise a buried insulating layer (not shown) on which may be formed the semiconductor layer 102. The semiconductor device 100 comprises a first device region 150N, which may represent a portion of the semiconductor layer 102, in and above which are a plurality of circuit elements 110n, such as field effect transistors, that represent a specific type of conductivity. For instance, the transistor elements 110n may represent N-channel transistors formed on the semiconductor layer 102 having an appropriate crystalline orientation so as to enable an increase of charge carrier mobility by creating a specific strain in the first device region 150N. Similarly, a second device region 150P may comprise a plurality of circuit elements 110p, such as transistors, wherein a different type of strain in the relevant portion of the semiconductor layer 102 may provide enhanced charge carrier mobility for the circuit elements 110p, which may therefore represent P-channel transistors. In the manufacturing stage shown in FIG. 1, a highly stressed dielectric material 103N is formed in the first device region 150N, wherein the material 103N may be comprised of silicon nitride and the like, as previously explained, and may induce the desired type of strain in the underlying portion of the semiconductor layer 102. Similarly, a second stressed dielectric material 103p is provided in the second device region 150P, wherein the internal stress of the material 103p may provide a desired type of strain. For example, the material 103p may be comprised of silicon nitride, nitrogen-containing silicon carbide and the like. Moreover, the semiconductor device 100 comprises an interlayer dielectric material 104, such as silicon dioxide, to passivate and enclose the circuit elements 110n, 110p in the first and second device regions 150N, 150P.
A typical process flow for forming the semiconductor device 100 may comprise the following processes. After the formation of the circuit elements 110n, 110p on the basis of well-established CMOS techniques, which may include the provision of further stress-inducing sources, such as the incorporation of strained semiconductor alloys, the application of stress memorization techniques and the like, the stress-inducing layers 103N, 103p may be formed on the basis of an appropriate patterning regime, as described above. That is, one of the layers 103N, 103p may be deposited first and may be subsequently removed from one of the device regions 150N, 150P, followed by the deposition of the other one of the layers 103p, 103N, for instance, including the deposition of an appropriate etch stop material (not shown), followed by a selective removal of a non-desired portion of the stress-inducing layer. Thereafter, the interlayer dielectric material 104 may be deposited on the basis of SACVD techniques, as previously discussed, and, thereafter, depending on the process strategy, a PECVD material may be deposited. In any case, a subsequent planarization process may be performed to enhance the surface topography of the device 100, wherein, however, a difference in height between the first and second device regions 150N, 150P may be observed, in particular in semiconductor devices corresponding to the 65 nm technology and beyond. For example, a difference in the thickness of the interlayer dielectric material 104 and thus a difference in height, indicated as 104D, may be observed between the first and second device regions 150N, 150P which may even remain after the planarization process. Consequently, during the subsequent lithography process and a complex contact etch process for forming respective contact openings, different process conditions may be encountered in the first and second device regions 150N, 150P, thereby resulting in non-uniformities of the contact openings and the finally obtained contacts after refilling the openings with a conductive material. Thus, the non-uniformity of the resulting contacts may lead to reduced production yield due to increased probability for contact failures of the device 100.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.